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MC100LVEL17DWR2 Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100LVEL17DWR2 Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 6 page MC100LVEL17 http://onsemi.com 2 D1 Figure 1. Logic Diagram and Pinout: (Top View) D1 D2 D3 17 18 16 15 14 13 12 4 3 5678 9 Q0 11 10 Q1 Q1 Q2 Q2 Q3 Q3 VEE D0 19 20 2 1 VCC Q0 D0 D2 VCC D3 VBB Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. * All VCC pins are tied together on the die. Table 1. PIN DESCRIPTION FUNCTION ECL Differential Data Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply PIN Dn, Dn Qn, Qn VBB VCC VEE Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 75 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 4 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 141 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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