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MC100LVEL01DR2G Scheda tecnica(PDF) 2 Page - ON Semiconductor |
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MC100LVEL01DR2G Scheda tecnica(HTML) 2 Page - ON Semiconductor |
2 / 7 page MC100LVEL01 http://onsemi.com 2 Figure 1. Logic Diagram and Pinout Assignment 1 2 3 4 5 6 7 8 D0 D1 D2 D3 VEE Q Q VCC PIN FUNCTION D0−D3 ECL Data Inputs Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply Table 1. PIN DESCRIPTION EP Exposed pad must be con- nected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V VI VCC VI VEE 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm 8 SOIC 8 SOIC 190 130 °C/W °C/W qJC Thermal Resistance (Junction to Case) Standard Board 8 SOIC 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm 8 TSSOP 8 TSSOP 185 140 °C/W °C/W qJC Thermal Resistance (Junction to Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder Pb Pb−Free <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. |
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