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MC100EPT622FAR2G Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC100EPT622FAR2G Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 4 1 Publication Order Number: MC100EPT622/D MC100EPT622 3.3VLVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The device has an OR−ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel−to−channel skew Features • 450 ps Typical Propagation Delay • Maximum Frequency > 1.5 GHz Typical • PECL Mode • Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • PNP LVTTL Inputs for Minimal Loading • Q Output Will Default HIGH with Inputs Open • The 100 Series Contains Temperature Compensation. • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAM* LQFP−32 FA SUFFIX CASE 873A 32 1 MC100 AWLYYWW EPT622 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week Table 1. TRUTH TABLE ENPECL H H ENTTL D Q X X L X X H H L H L H L X H L H L L See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ORDERING INFORMATION http://onsemi.com |
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