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MC100EPT23DR2 Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC100EPT23DR2 Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 15 1 Publication Order Number: MC100EPT23/D MC100EPT23 3.3VDual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock or data signal. The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the EPT23 does not require both ECL standard versions. The LVPECL/LVDS inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL/LVDS input referenced from a VCC of +3.3 V. Features • 1.5 ns Typical Propagation Delay • Maximum Operating Frequency > 275 MHz • LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs • 24 mA LVTTL Outputs • Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V • Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAMS* A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package KA23 ALYW G G SOIC−8 D SUFFIX CASE 751 1 8 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION http://onsemi.com KPT23 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 (Note: Microdot may be in either location) |
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