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MC74VHCT139AMELG Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC74VHCT139AMELG Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 4 1 Publication Order Number: MC74VHCT139A/D MC74VHCT139A Dual 2−to−4 Decoder/ Demultiplexer The MC74VHCT139A is an advanced high speed CMOS 2−to−4 decoder/demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL devices while maintaining CMOS low power dissipation. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operations. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device output is compatible with TTL−type input thresholds and the output has a full 5.0 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic to 3.0 V CMOS logic while operating at the high−voltage power supply The MC74VHCT139A input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74VHCT139A to be used to interface 5.0 V circuits to 3.0 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage−input/output voltage mismatch, battery backup, hot insertion, etc. Features • High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V • Low Power Dissipation: ICC = 4 mΑ (Max) at TA = 25°C • TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Designed for 2.0 V to 5.5 V Operating Range • Low Noise: VOLP = 0.8 V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300 mA • ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V • Chip Complexity: 100 FETs or 25 Equivalent Gates • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAMS TSSOP−16 DT SUFFIX CASE 948F SOIC−16 D SUFFIX CASE 751B See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION http://onsemi.com A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb−Free Package VHCT139AG AWLYWW VHCT 139A ALYW G G (Note: Microdot may be in either location) 1 1 16 1 1 16 1 SOEIAJ−16 M SUFFIX CASE 966 74VHCT139 ALYWG 1 16 FUNCTION TABLE Inputs Outputs E A1 A0 Y0 Y1 Y2 Y3 HX X H H H H LL L L H H H LL H H L H H LH L H H L H LH H H H H L |
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