MC100EL38DWR2G datasheet(5/7 Pages) ONSEMI

Il numero della parte	MC100EL38DWR2G

Spiegazioni elettronici	5V ECL 첨2, 첨4/6 Clock Generation Chip

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MC100EL38

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5

CLK

Q (P2)

Q (P4)

Q (P6)

Phase_Out (P4)

Phase_Out (P6)

Figure 3. Timing Diagram

MR

tRR

Figure 4. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

QD

Q

D

Zo = 50 W

50 W

VTT

VTT = VCC − 2.0 V

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