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MV1403 Scheda tecnica(PDF) 6 Page - Zarlink Semiconductor Inc |
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MV1403 Scheda tecnica(HTML) 6 Page - Zarlink Semiconductor Inc |
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6 / 18 page  MV1403 5 TRANSMIT DEMONSTRATION MODE, TX2 Transmit demonstration mode (MODE =0, DEMO= I) uses the four transmitter macrocells connected together internally, to demonstrate how they may be utilised to perform the common channel signalling and error detection functions of a 2.048 Mbit 30 channel PCM transmitter. The functional diagram of the MV1403 in this mode is now as shown in Fig. 6. Again all four macrocells are synchronised to a common 2.048MHz clock with frame synchronisation achieved from the FRS input. The Timeslot Zero transmitter alternately outputs sync words and non-sync words, during timeslot zero, denoting which by its TZS output. The user data bits of the nonsync word (D3N-D8N) are available as parallel data inputs. The Timeslot Zero data is used as one of the inputs to the transmission multiplexer. The Timeslot Sixteen transmitter takes in the continuous 64kbit data stream from its D input and outputs this in 8 bit bursts during timeslot 16. This data along with the TS16 frame marker are also used as inputs to the transmission multiplexer, TMUX. The transmission multiplexer forms a single PCM data stream at its Q output by multiplexing the timeslot zero and timeslot 16 data with the remaining 30 channels (timeslots 1- 15 and 17-31) of voice data. This is controlled by the two frame marker inputs to the multiplexer, FRS and TS16. The output from TMUX is input to the Cyclic Redundancy Check Generator and HDB3 Encoder macrocells. When in CRC mode (EN=1), the CRC Generator macrocell performs its CRC procedure on this incoming data stream. In non-CRC mode, this macrocell uses its two data inputs, D1S and D1N, along with the timing input, TZS, to determine its output. However, in CRC mode the output consists ol the CRC word data bits interleaved with the CRC multiframe alignment word and the two user data bits, D1S and D1N, as previously displayed in Table 2. In either case, the output data is input directly to the international spare bit input of the Timeslot Zero Transmitter. The TZS input of the CRC generator is connected directly to the TZS output of the Timeslot Zero Transmitter. The output data from the transmission multiplexer is also input to the HDB3 Encoder macrocell. This macrocell converts the incoming NRZ data into pseudo-ternary HDB3 transmission code, ensuring adequate clock recovery at the receiver. This data is output on the TXD1 and TXD2 output pins. The Q output of the HDB3 Encoder macrocell is a single period delayed version of its D input and as such allows the output from the transmission multiplexer to be observed. Fig. 6 shows that all of the intemal connections except the output from TMUX, are also available as outputs from the MV1403, allowing the interaction of the rnacrocells to be observed. CLK MODE STM DEMO CRC EN (CRC) VDD GND MFQ6 MFD4 MFD2 MFQ3 MFQ4 MFQ5 MFQ8 MFQ9 MFD6 MFQ1 MFQ2 DQ3-DQ8 FRS FRS CLK TZS D Q D1S D1N D3N-D8N Q D Q TS16 TXD1 TXD2 MODE CONTROL TXTSZ CRCGEN HDB3EC TXTS16 TMUX D VDD STM DEMO MODE CLK Q TZS MFD1 PCM DATA Q Figure 6: TX2 Transmit demonstration mode functional diagram |
Codice articolo simile - MV1403 |
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Descrizione simile - MV1403 |
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