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MC100EP105FAR2 Scheda tecnica(PDF) 1 Page - ON Semiconductor

Il numero della parte MC100EP105FAR2
Spiegazioni elettronici  3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND
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© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 11
1
Publication Order Number:
MC10EP105/D
MC10EP105, MC100EP105
3.3V / 5VECL Quad 2−Input
Differential AND/NAND
Description
The MC10/100EP105 is a quad 2−input differential AND/NAND
gate. Each gate is functionally equivalent to the EP05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP105 is ideal for applications requiring the fastest AC
performance available.
The 100 Series contains temperature compensation.
Features
275 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
LQFP−32
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
MCxxx
EP105
AWLYYWWG
xxx
= 10 or 100
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
QFN32
MN SUFFIX
CASE 488AM
32
1
MCxxx
EP105
AWLYYWWG
G
1
(Note: Microdot may be in either location)


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