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MC10EL35D Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC10EL35D Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 6 1 Publication Order Number: MC10EL35/D MC10EL35, MC100EL35 5VECL JK Flip-Flop Description The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation. Features • 525 ps Propagation Delay • 2.2G Hz Toggle Frequency • ESD Protection: > 1 kV Human Body Model, > 100 V Machine Model • PECL Mode Operating Range: VCC = 4.2 V to 5.7 with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input Pulldown Resistors on J, K, CLK, and R • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL−94 V−0 @ 0.125 in, Oxygen Index 28 to 34 • Transistor Count = 81 devices • Pb−Free Packages are Available *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAMS* KL35 ALYWG G SOIC−8 D SUFFIX CASE 751 1 8 TSSOP−8 DT SUFFIX CASE 948R 1 8 1 8 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION http://onsemi.com KEL35 ALYW G 1 8 DFN8 MN SUFFIX CASE 506AA 14 14 HL35 ALYWG G 1 8 HEL35 ALYW G 1 8 (Note: Microdot may be in either location) H = MC10 K = MC100 4W = MC10 2L = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package |
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