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FIN324CMLX Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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FIN324CMLX Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 23 page March 2007 © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN324C Rev. 1.0.5 FIN324C 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays Features Ultra-Low Operating Power: ~4mA at 5.44MHz Supports Dual-Display Implementations with RGB or Microcontroller Interface No External Timing Reference Needed SPI Mode Support Single Device Operates as a Serializer or Deserializer Direct Support for Motorola ®-Style R/W Microcontroller Interface Direct Support for Intel ®-Style /WE, /RE Microcontroller Interface 15MHz Maximum Strobe Frequency Utilizes Fairchild’s Proprietary CTL Serial I/O Technology Available in BGA and MLP packages Wide Parallel Supply Voltage Range: 1.60 to 3.0V Low Power Core Operation: VDDS/A=2.5 to 3.0V Voltage Translation Capability Across Pair with No External Components High ESD protection: >14.5kV HBM Power-Saving Burst-Mode Operation Applications Single or Dual 16/18-Bit RGB Cell Phone Displays Single or Dual 16/18-Bit Cell Phone Displays with Microcontroller Interface Single or Dual Mobile Display at QVGA or HVGA Resolution Description The FIN324C is a 24-bit serializer / deserializer with dual strobe inputs. The device can be configured as a master or slave device through the master/slave select pin (M/S). This allows for the same device to be used as either a serializer or deserializer, minimizing component types in the system. The dual strobe inputs allow implementation of dual-display systems with a single pair of µSerDes. The FIN324C can accommodate RGB, microcontroller, or SPI mode interfaces. Read and write transactions are supported when operating with a Motorola-style microcontroller interface for one or both displays. Unlike other SerDes solutions, no external timing reference is required for operation. The FIN324C is designed for ultra-low power operation. Reset (/RES) and standby (/STBY) signals put the device in an ultra-low power state. In standby mode, the outputs of the slave device maintain state, allowing the system to resume operation from the last-known state. The device utilizes Fairchild’s proprietary ultra-low power, low-EMI Current Transfer Logic™ (CTL) technology. The serial interface disables between transactions to minimize EMI at the fundamental serial interface and to conserve power. LV-CMOS parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize EMI. The serialization bit clock is generated internally to the FIN324C. The minimum bit clock frequency is always great enough to handle the maximum strobe frequency. Related Application Notes AN-5058 µSerDes™ Family Frequently Asked Questions AN-5061 µSerDes™ Layout Guidelines AN-6047 FIN324C Reset and Standby |
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