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AD9882A Scheda tecnica(PDF) 1 Page - Analog Devices |
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AD9882A Scheda tecnica(HTML) 1 Page - Analog Devices |
1 / 40 page Dual Interface for Flat Panel Displays AD9882A Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES Analog interface 140 MSPS maximum conversion rate Programmable analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 140 MSPS 3.3 V power supply Full sync processing Midscale clamping 4:2:2 output format mode Digital interface DVI 1.0 compatible interface 112 MHz operation High skew tolerance of 1 full input clock Sync detect for hot plugging Supports high bandwidth digital content protection APPLICATIONS RGB graphics processing LCD monitors and projectors Plasma display panels Scan converter Microdisplays Digital TV FUNCTIONAL BLOCK DIAGRAM A/D CLAMP RAIN GAIN BAIN SOGIN HSYNC SYNC PROCESSING AND CLOCK GENERATION FILT VSYNC SCL SDA A0 RX0+ RX0– RX1+ RX1– RX2+ RX2– RXC+ RXC– RTERM DDCSCL DDCSDA MCL MDA 8 A/D CLAMP 8 A/D CLAMP 8 ANALOG INTERFACE DATACK HSOUT VSOUT SOGOUT 8 REF ROUT GOUT BOUT ROUT GOUT BOUT ROUT GOUT BOUT DATACK DE HSYNC VSYNC DATACK HSOUT CSOUT SOGOUT DE REFBYPASS 8 8 DVI RECEIVER HDCP 8 8 8 AD9882A SERIAL REGISTER AND POWER MANAGEMENT DIGITAL INTERFACE Figure 1. GENERAL DESCRIPTION The AD9882A offers designers the flexibility of an analog inter- face and a digital visual interface (DVI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP). Analog Interface The AD9882A is a complete, 8-bit, 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz sup-ports resolutions up to SXGA (1280 × 1024 at 75 Hz). The analog interface includes a 140 MHz triple ADC with internal 1.25 V reference, a phase-locked loop (PLL), program- mable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync. Three-state CMOS outputs can be powered from 2.2 V to 3.3 V. The AD9882A’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882A also offers full sync processing for composite sync and sync-on-green (SOG) applications. Digital Interface The AD9882A contains a DVI 1.0 compatible receiver and supports display resolutions up to SXGA (1280 × 1024 at 60 Hz). The receiver features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can now receive encrypted video content. The AD9882A allows for authentica- tion of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during trans- mission, as specified by the HDCP v1.0 protocol. It also has high tolerance of noncompliant HDCP sources. Fabricated in an advanced CMOS process, the AD9882A is provided in a space-saving, 100-lead LQFP surface-mount plastic package and is specified over the 0°C to 70°C temperature range. It is available in a Pb-free package. |
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