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AD9211BCPZ-170 Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD9211BCPZ-170 Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 21 page AD9211 Preliminary Technical Data Rev. PrA | Page 6 of 21 SWITCHING SPECIFICATIONS Table 4. (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, DCS Enabled unless otherwise noted.) AD9211-170/-200 AD9211-250 Parameter (Conditions) Temp Min Typ Max Min Typ Max Unit Maximum Conversion Rate1 Full 170/200 250 MSPS Minimum Conversion Rate1 Full 40 40 MSPS CLK+ Pulsewidth High (tEH)1 Full TBD TBD ns CLK+ Pulsewidth Low (tEL)1 Full TBD TBD ns OUTPUT (LVDS) Valid Time (tV) Full TBD TBD ns Propagation Delay (tPD) Full 3.9 3.9 ns Rise Time (tR) (20% to 80%) 25°C 0.4 0.4 ns Fall Time (tF) (20% to 80%) 25°C 0.4 0.4 ns DCO Propagation Delay (tCPD) Full 3.2 3.2 ns Data to DCO Skew (tPD– tCPD) Full TBD TBD ns Latency (L) Full 5 5 Cycles Aperture Delay (tA) 25°C TBD TBD ns Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms Out of Range Recovery Time 25°C TBD TBD Cycles 1 All ac specifications tested by driving CLK+ and CLK– differentially. N–1 N N+1 N+L N+L+1 N+L+2 N+L+3 tEH tEL 1/fS tA N–L tPD L CYCLES tV N-L+1 N N+1 N+2 tCPD CLK+ CLK– DATA OUT DCO– DCO+ AIN Figure 2. Timing Diagram (L=5 Cycles) |
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