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DM74S257 Scheda tecnica(PDF) 1 Page - National Semiconductor (TI) |
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DM74S257 Scheda tecnica(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page TLF6482 June 1989 DM54S257DM74S257 DM54S258DM74S258 TRI-STATE Quad 1 of 2 Data SelectorsMultiplexers General Description These Schottky-clamped high-performance multiplexers feature TRI-STATE outputs that can interface directly with data lines of bus-organized systems With all but one of the common outputs disabled (at a high impedance state) the low impedance of the single enabled output will drive the bus line to a high or low logic level To minimize the possibil- ity that two outputs will attempt to take a common bus to opposite logic levels the output enable circuitry is designed such that the output disable times are shorter than the out- put enable times This TRI-STATE output feature means that n-bit (paralleled) data selectors with up to 258 sources can be implemented for data buses It also permits the use of standard TTL reg- isters for data retention throughout the system Features Y TRI-STATE versions S157 S158 with same pin-outs Y Schottky-clamped for significant improvement in A-C performance Y Provides bus interface from multiple sources in high- performance systems Y Average propagation delay from data input S257 48 ns S258 4 ns Y Typical power dissipation S257 320 mW S258 280 mW Connection Diagrams Dual-In-Line Package TLF6482 – 1 Dual-In-Line Package TLF6482 – 2 Order Number DM54S257J DM54S258J DM54S257W DM74S257N or DM74S258N See NS Package Number J16A N16E or W16A Function Table Inputs Output Y Output Select A B S257 S258 Control HX X X Z Z LL L X L H LL H X H L LH X L L H LH X H H L H e High Level L e Low Level X e Don’t Care Z e High Impedance (off) TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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