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ADF7021 Scheda tecnica(PDF) 5 Page - Analog Devices

Il numero della parte ADF7021
Spiegazioni elettronici  High Performance Narrowband ISM Transceiver IC
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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Preliminary Technical Data
ADF7021
Rev. PrI | Page 5 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions
CHANNEL FILTERING
Adjacent Channel Rejection
(Offset = ±1 × IF Filter BW Setting)
27
dB
IF filter BW setting = 12.5 kHz, 18.75 kHz, 25 kHz
Second Adjacent Channel Rejection
(Offset = ±2 × IF Filter BW Setting)
50
dB
Desired signal 3 dB above the input sensitivity
level, CW interferer power level
Third Adjacent Channel Rejection
(Offset = ±3 × IF Filter BW Setting)
55
dB
Increased until BER = 10−3, image channel
excluded
Image Channel Rejection
35
dB
Image at FRF − 200 kHz
Co-Channel Rejection
−3
dB
Wideband Interference Rejection
70
dB
Swept from 100 MHz to 2 GHz, measured as
channel rejection
BLOCKING
±1 MHz
60
dB
Desired signal 3 dB above the input sensitivity
level, CW interferer power level
±5 MHz
68
dB
Increased until BER = 10−2
±10 MHz
65
dB
±10 MHz (High Linearity Mode)
72
dB
Saturation (Maximum Input Level)
12
dBm
FSK mode, BER = 10−3
LNA Input Impedance
24 − j60
Ω
FRF = 915 MHz, RFIN to GND
26 − j63
Ω
FRF = 868 MHz
71 − j128
Ω
FRF = 433 MHz
RECEIVE SIGNAL STRENGTH INDICATOR (RSSI)
Range at Input
−110 to −36
dBm
Linearity
±2
dB
Absolute Accuracy
±3
dB
Response Time
150
μs
See the RSSI/AGC section
PHASE-LOCKED LOOP (PLL)
VCO Gain
65
MHz/V
902 MHz to 928 MHz band, VCO adjust = 0,
VCO_BIAS_SETTING = 8
130
MHz/V
860 MHz to 870 MHz band, VCO adjust = 0
65
MHz/V
433 MHz, VCO adjust = 0
Phase Noise (In-Band)
−99
dBc/Hz
PA = 10 dBm, VDD = 3.0 V, PFD = 24.57 MHz,
FRF = 433 MHz, VCO_BIAS_SETTING = 15
Phase Noise (Out-of-Band)
−113
dBc/Hz
1 MHz offset
Residual FM
128
Hz
From 200 Hz to 20 kHz, FRF = 868 MHz
PLL Settling
40
μs
Measured for a 10 MHz frequency step to
within 5 ppm accuracy, PFD = 20 MHz,
loop bandwidth (LBW) = 50 kHz
REFERENCE INPUT
Crystal Reference
3.625
TBD
MHz
External Oscillator
3.625
TBD
MHz
Load Capacitance
33
pF
PC board layout and crystal specific
Crystal Start-Up Time
2.1
ms
11.0592 MHz crystal, using 33 pF load capacitors
Input Level
CMOS
levels
See the Reference Input section
ADC PARAMETERS
INL
±1
LSB
From 2.3 V to 3.6 V, TA = 25°C
DNL
±1
LSB
From 2.3 V to 3.6 V, TA = 25°C
TIMING INFORMATION
Chip Enabled to Regulator Ready
10
μs
CREG = 100 nF
Chip Enabled to RSSI Ready
3.0
ms
See Table 14 for more details
Tx to Rx Turnaround Time
150 μs +
(5 × TBIT)
Time to synchronized data out, includes AGC
settling; see AGC Information and Timing
section for more details


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