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AD9889PCB Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD9889PCB Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 12 page AD9889A Rev. 0 | Page 6 of 12 Pin No. Mnemonic Type1 Description F9 SDA C2 Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. F10 SCL C2 Serial Port Data Clock. This pin serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. E10 MDA C2 Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. E9 MCL C2 Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. G9 DDCSDA C2 Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. 5 V CMOS logic level. G10 DDCSCL C2 Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. 5 V CMOS logic level. 1 I = input, O = output, P = power supply, C = control. 2 For a full description of the 2-wire serial interface and its functionality obtain documentation by contacting NDA from flatpanel_apps@analog.com. |
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