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MC74ACT377N Scheda tecnica(PDF) 1 Page - Motorola, Inc |
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MC74ACT377N Scheda tecnica(HTML) 1 Page - Motorola, Inc |
1 / 6 page 5-1 FACT DATA Octal D FlipFlop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip- flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. • Ideal for Addressable Register Applications • Clock Enable for Address and Data Synchronization Applications • Eight Edge-Triggered D Flip-Flops • Buffered Common Clock • Outputs Source/Sink 24 mA • See MC74AC273 for Master Reset Version • See MC74AC373 for Transparent Latch Version • See MC74AC374 for 3-State Version • ′ACT377 Has TTL Compatible Inputs 19 20 18 17 16 15 14 2 1 3 4 5 6 7 VCC 13 8 12 9 11 10 O7 D7 D6 O6 O5 D5 D4 O4 CP CE O0 D0 D1 O1 O2 D2 D3 O3 GND PIN NAMES D0–D7 Data Inputs CE Clock Enable (Active LOW) Q0–Q7 Data Outputs CP Clock Pulse Input MODE SELECT-FUNCTION TABLE Operating Mode Inputs Outputs Operating Mode CP CE Dn Qn Load ′1′ L H H Load ′0′ L L L Hold (Do Nothing) H X No Change Hold (Do Nothing) X H X No Change H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition MC74AC377 MC74ACT377 OCTAL D FLIP-FLOP WITH CLOCK ENABLE N SUFFIX CASE 738-03 PLASTIC DW SUFFIX CASE 751D-04 PLASTIC LOGIC SYMBOL O0 O1 O2 O3 O4 O5 O6 O7 D0 D1 D2 D3 D4 D5 D6 D7 CP CE |
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