MOTOROLA CMOS LOGIC DATA

1

MC14530B

Dual 5-Input Majority

Logic Gate

The MC14530B dual five–input majority logic gate is constructed with

P–channel and N–channel enhancement mode devices in a single

monolithic structure. Combinational and sequential logic expressions are

easily implemented with the majority logic gate, often resulting in fewer

components than obtainable with the more basic gates. This device can also

provide numerous logic functions by using the W and some of the logic (A

thru E) inputs as control inputs.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, Vout Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

Iin, Iout

Input or Output Current (DC or Transient),

per Pin

± 10

mA

PD

Power Dissipation, per Package†

500

mW

Tstg

Storage Temperature

– 65 to + 150

_C

TL

Lead Temperature (8–Second Soldering)

260

_C

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/

_C From 100_C To 125_C

LOGIC TABLE

INPUTS A B C D E

W

Z

For all combinations of inputs where three or

more inputs are logical “0”.

0

1

more inputs are logical “0”.

1

0

For all combinations of inputs where three or

more inputs are logical “1”.

0

0

more inputs are logical “1”.

1

1

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must

be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, Vin and

Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 3

1/94

MC14530B

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP

Plastic

MC14XXXBCL

Ceramic

MC14XXXBD

SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

BLOCK DIAGRAM

TRUTH TABLE

M5

W

Z

0

0

1

0

1

0

1

0

0

1

1

1

VDD = PIN 16

VSS = PIN 8

A

W

1

B

C

D

E

2

3

4

5

6

Z

7

M5

A

B

C

D

E

M5

13

12

11

10

9

14

W

Z

15

* Z = M5  W = (ABC+ABD+ABE+ACD+

* M5 is a logical “1” if any three or more

inputs are logical “1”.

  Exclusive NOR  Exclusive OR