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74LVC169 Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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74LVC169 Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
4 / 14 page Philips Semiconductors Product specification 74LVC169 Presettable synchronous 4-bit up/down binary counter 1998 May 20 4 STATE DIAGRAM 0 123 4 5 6 7 8 9 10 11 12 13 14 15 COUNT DOWN COUNT UP SF00788 FUNCTION TABLE OPERATING INPUTS OUTPUTS MODES CP U/D CEP CET PE Dn Qn TC Parallel load (Dn →Qn) ↑ X X X l l L * ↑ X X X X X H * Count Up (increment) ↑ h l l h X Count Up * Count Down (decrement) ↑ l l l h X Count Down * Hold (do nothing) ↑ X h X h X qn * ↑ X X X h X qn H H = High voltage level steady state h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level steady state l = Low voltage level one setup time prior to the Low-to-High clock transition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition * = The TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL). TYPICAL TIMING SEQUENCE CP PE TC MR INHIBIT COUNT CEP CET D0 D2 D1 D3 Q0 Q2 Q1 Q3 RESET PRESET 12 13 14 15 0 1 2 SY00069 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one, and two; inhibit |
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