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74LVC162373ADGG Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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74LVC162373ADGG Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
11 / 17 page 2004 Feb 05 11 Philips Semiconductors Product specification 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state 74LVC162373A; 74LVCH162373A AC WAVEFORMS mna429 nDn input nQn output tPLH tPHL GND VI VM VM VOH VOL Fig.6 Input (nDn) to output (nQn) propagation delays. VOL and VOH are the typical output voltage drop that occur with the output load. VCC VM INPUT VI tr =tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns mna430 nLE input nQn output tPHL tW GND VI VM VM VOH VOL tPLH Fig.7 Latch enable input (nLE) pulse width, and the latch enable input to output (nQn) propagation delays. VOL and VOH are the typical output voltage drop that occur with the output load. VCC VM INPUT VI tr =tf 1.2 V 0.5 × VCC VCC ≤ 2.5 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns |
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