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74LVC07APW Scheda tecnica(PDF) 2 Page - NXP Semiconductors

Il numero della parte 74LVC07APW
Spiegazioni elettronici  Hex buffer with open-drain outputs
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Produttore elettronici  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC07APW Scheda tecnica(HTML) 2 Page - NXP Semiconductors

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2000 Mar 07
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Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
FEATURES
• 5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
• Wide supply voltage range from 1.65 to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Complies with JEDEC standard no. 8-1A.
DESCRIPTION
The 74LVC07A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. This feature allows
the use of these devices as translators in a mixed
3.3 to 5 V environment.
The 74LVC07A provides six non-inverting buffers.
The outputs of the 74LVC07A devices are open drain and
can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH
wired-AND functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of the outputs.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
tPLZ/tPZL
propagation delay nA to nY
CL = 50 pF; VCC = 3.3 V
2.2
ns
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per gate
VI = GND to VCC; note 1
6.0
pF
INPUT
OUTPUT
nA
nY
LL
HZ


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