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74LV573PWDH Scheda tecnica(PDF) 8 Page - NXP Semiconductors |
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74LV573PWDH Scheda tecnica(HTML) 8 Page - NXP Semiconductors |
8 / 14 page Philips Semiconductors Product specification 74LV573 Octal D-type transparent latch (3-State) 1998 Jun 10 8 AC WAVEFORMS VM = 1.5V at VCC w 2.7V and v 3.6V VM = 0.5 * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V and v 3.6V VX = VOL + 0.1VCC at VCC < 2.7V and w 4.5V VY = VOH – 0.3V at VCC w 2.7V and v 3.6V VY = VOH – 0.1VCC at VCC < 2.7V and w 4.5V SV00705 VM Dn INPUT VI GND VOH VOL Qn OUTPUT VM tPLH tPHL Figure 1. Data input (Dn) to output (Qn) propagation delays and the output transition times SV00706 VM LE INPUT VI GND VOL VOH Qn OUTPUT VM tPLH tPHL tW Figure 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. SV00664 outputs disabled outputs enabled outputs enabled tPHZ tPZH tPZL tPLZ VX VY VM VM VM OE INPUT VI VCC VOL VOH GND GND Qn OUTPUT LOW-to-OFF OFF-to-LOW Qn OUTPUT HIGH-to-OFF OFF-to-HIGH Figure 3. 3-State enable and disable times SV00665 VM Dn INPUT LE INPUT GND GND VI VI VM tsu tsu th th NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 4. Data set-up and hold times for the Dn input to the LE input NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT SWITCH POSITION PULSE GENERATOR RT VI D.U.T. VO CL RL = 1k VCC Test Circuit for Outputs DEFINITIONS VCC VI < 2.7V VCC TEST tPLH/tPHL RT = Termination resistance should be equal to ZOUT of pulse generators. 2.7V 2.7–3.6V w 4.5V VCC 50 pF SV00896 S1 tPLZ/tPZL tPHZ/tPZH Open 2 * VCC GND RL = 1k Open 2 * VCC GND RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. Figure 5. Load circuitry for switching times |
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