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74HCT6323A Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74HCT6323A Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 15 page September 1993 2 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A FEATURES • 8-pin space saving package • Programmable 3-stage ripple counter • Suitable for over-tone crystal application up to 50 MHz (VCC =5V ± 10%) • 3-state output buffer • Two internal capacitors • Recommended operating range for use with third overtone crystals 3to6V • Oscillator stop function (MR) • Output capability: bus driver → (15 LSTTL) • ICC category: MSI. APPLICATIONS • Control counters • Timers • Frequency dividers • Time-delay circuits • CIO (Compact Integrated Oscillator) • Third-overtone crystal operation. GENERAL DESCRIPTION The HC/HCT6323A are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT6323A are oscillators designed for quartz crystal combined with a programmable 3-state counter, a 3-state output buffer and an overriding asynchronous master reset (MR). With the two select inputs S1 and S2 the counter can be switched in the divide-by-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The oscillator is designed to operate either in the fundamental or third overtone mode depending on the crystal and external components applied. On-chip capacitors minimize external component count for third overtone crystal applications. The oscillator may be replaced by an external clock signal at input X1. In this event the other oscillator pin (X2) must be floating. The counter advances on the negative-going transition of X1. A LOW level on MR resets the counter, stops the oscillator and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where: fi = input frequency in MHz; fo = output frequency in MHz. VCC = supply voltage in V; CL = output load capacitance in pF. Ipull-up = pull-up currents in µA. 2. For HC and HCT an external clock is applied to X1 with: tr = tf ≤ 6 ns, Vi is GND to VCC, MR = HIGH Ipull-up is the summation of −II (µA) of S1 and S2 inputs at the LOW state. ORDERING INFORMATION SYMBOL PARAMETER CONDITIONS TYP. UNIT HC HCT tPHL/tPLH propagation delay X1 to OUT (S1 = S2 = LOW) CL = 15 pF; VCC = 5 V 17 17 ns fmax maximum clock frequency 90 90 MHz CI input capacitance except X1 and X2 3.5 3.5 pF CPD power dissipation capacitance per package +1; notes 1 and 2 54 54 pF +2; notes 1 and 2 42 42 pF +4; notes 1 and 2 36 36 pF +8; notes 1 and 2 33 33 pF EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE 74HC/HCT6323AD 8 SO plastic SOT96 |
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