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74HCT4059D Scheda tecnica(PDF) 11 Page - NXP Semiconductors |
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74HCT4059D Scheda tecnica(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 1998 Jul 08 11 Philips Semiconductors Product specification Programmable divide-by-n counter 74HC/HCT4059 AC WAVEFORMS Fig.7 Waveforms showing the clock (CP) to output (Q) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the LE input to Q output propagation delay. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the Kb or Kc removal times, when the operating mode is switched from master preset to any other mode. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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