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74HCT4066 Scheda tecnica(PDF) 2 Page - NXP Semiconductors |
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74HCT4066 Scheda tecnica(HTML) 2 Page - NXP Semiconductors |
2 / 24 page 1998 Nov 10 2 Philips Semiconductors Product specification Quad bilateral switches 74HC/HCT4066 FEATURES • Very low “ON” resistance: 50 Ω (typ.) at VCC = 4.5 V 45 Ω (typ.) at VCC = 6.0 V 35 Ω (typ.) at VCC = 9.0 V • Output capability: non-standard • ICC category: SSI. GENERAL DESCRIPTION The 74HC/HCT4066 are high-speed Si-gate CMOS devices and are pin compatible with the “4066” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4066 have four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH enable input (nE). When nE is LOW the belonging analog switch is turned off. The “4066” is pin compatible with the “4016” but exhibits a much lower “ON” resistance. In addition, the “ON” resistance is relatively constant over the full input signal range. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf =6ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): a) PD =CPD × VCC2 × fi +∑ {(CL + CS)× VCC2 × fo} where: b) fi = input frequency in MHz c) fo = output frequency in MHz d) ∑ {(CL + CS)× VCC2 × fo} = sum of outputs e) CL = output load capacitance in pF f) CS = maximum switch capacitance in pF g) VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPZH/ tPZL turn-on time nE to Vos CL = 15 pF; RL =1kΩ; VCC = 5 V 11 12 ns tPHZ/ tPLZ turn-off time nE to Vos 13 16 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per switch notes 1 and 2 11 12 pF CS max. switch capacitance 8 8 pF |
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