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TP-UART-IC Scheda tecnica(PDF) 7 Page - Siemens Semiconductor Group

Il numero della parte TP-UART-IC
Spiegazioni elettronici  TP-UART-IC
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Produttore elettronici  SIEMENS [Siemens Semiconductor Group]
Homepage  http://www.siemens.com/
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TP-UART-IC
The reproduction, transmission or use of this document or it‘s contents is not permitted without express written authority. All
rights, including right created by patent grant or registration of a utility model or design, are reserved. Technical changes
reserved.
25.15.10.41.33a
25.10.01
page
7
1.2.11 Interface Pin TxD (Pin 1)
The UART interface output pin TxD transmits the information to host controller. The high
output level is derived from external voltage supply VIF. This pin is ESD protected to VB-
and VIF.
In normal mode: LOW pulse at EIB bus
à TxD3 = HIGH à TxD = LOW
In analog mode: LOW pulse at EIB bus
à TxD3 = HIGH à TxD = HIGH
Symbol
Parameter
Min
Max
Unit
Note
VOH
output voltage high
VIF - 0.8
V
IOH = -5 mA
VOL
output voltage low
0.5
V
IOL = 5 mA
tr, tf
rise time, fall time (10 %
↔ 90 %)
100
ns
CL = 150 pF
1.2.12 Reset Pin RESn (Pin 2)
This pin is an I / O pin with internal pull - up resistor to VIF.
In case of a reset the reset pin RESn delivers an active LOW signal to external host
controller. The output driver is realized as open drain (NMOS - transistor). The reset state
RESn = LOW can be caused by an internal RESET or by an external RESET due to forcing
an active LOW to the pin RESn. The switching levels are derived from external voltage
supply VIF. This pin is ESD protected to VB - and VIF.
Symbol Parameter
Min
Max
Unit
Note
RPullUp
value of internal pull-up resistor to VIF
10
25
k
VRESmax
maximum voltage at RES pin
VIF + 0.5
V
VIL
voltage range for input low level
0
0.2 * VIF
VIH
voltage range for input high level
0.8 * VIF
1.0 * VIF
Vhyst
hysteresis for switching level
0.1 * VIF
0.4 * VIF
1)
VOL
output low voltage at 1V <= VCC < 4 V, IOL = 1 mA
0.2
V
VOL
output low voltage at VCC <= 1V, VIF > 3 V,
IOL = 1 mA
0.2
V
VOL
output low voltage at VCC >= 4 V, IOL = 3 mA
0.4
V
1) Switching level appr. VIF/2, i.e. VIF/2
±V
hyst/2
1.2.13 Save PIN SAVE (Pin 5)
This pin is an NMOS open drain output with internal pullup resistor to VIF.
In case of break-down of the bus voltage for more than typ. 1.5 ms (save condition) this pin
delivers an active LOW signal to external host electronic. This pin is ESD protected to VB-
and VIF.
Symbol
Parameter
Min
Max
Unit
Note
RPullUp
Value of internal pull-up resistor to VIF
10
25
k
Vmax
maximum voltage at SAVE pin
VIF + 0.5
V
VOL
Output LOW voltage at VCC >= 4V
0.4
V
IOL = 3 mA
tFRG2
Delay from VB+ break-down to SAVE= LOW
0.7
3
ms
Typ. 1.5 ms
In order to reach a Buffertime of at least 60 ms for VCC (IVCC
≤10 mA) the capacitor at VSP has to
be 470
µF ±20 %


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