Philips Semiconductors

Product specification

74ABT845

8-bit bus interface latch with set and reset

(3-State)

1

1995 Sep 06

853-1703 15702

FEATURES

required with MOS microprocessors

and 200 V per Machine Model

DESCRIPTION

The 74ABT845 consists of eight D-type latches with 3-State outputs.

In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two

additional OE pins, making a total of three Output Enable (OE0,

OE1, OE2) pins. The multiple Output enables allow multiuser control

of the interface, e.g., CS, DMA, and RD/WR.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay

Dn to Qn

5.4

ns

Input capacitance

4

pF

Output capacitance

Outputs disabled;

7

pF

Total supply current

500

nA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

24-Pin Plastic DIP

–40

°C to +85°C

74ABT845 N

74ABT845 N

SOT222-1

24-Pin plastic SO

–40

°C to +85°C

74ABT845 D

74ABT845 D

SOT137-1

24-Pin Plastic SSOP Type II

–40

°C to +85°C

74ABT845 DB

74ABT845 DB

SOT340-1

24-Pin Plastic TSSOP Type I

–40

°C to +85°C

74ABT845 PW

74ABT845PW DH

SOT355-1

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10

15

16

17

18

19

20

21

22

23

24

OE0

OE1

D0

D1

D2

D3

D4

D5

D6

Q6

D7

Q5

Q4

Q3

Q2

Q1

Q0

OE2

VCC

Q7

11

14

MR

PRE

12

13

GND

LE

TOP VIEW

SA00258

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

1, 2, 23

OE0 – OE2

Output enable inputs

(active-Low)

3, 4, 5, 6,

7, 8, 9, 10

D0-D7

Data inputs

22, 21, 20, 19,18,

17, 16, 15

Q0-Q7

Data outputs

11

MR

Master reset input (active-Low)

13

LE

Latch enable input

(active-High)

14

PRE

Preset input (active-Low)

12

GND

Ground (0V)

24

Positive supply voltage