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ADF7025BCPZ-RL Scheda tecnica(PDF) 5 Page - Analog Devices |
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ADF7025BCPZ-RL Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 44 page ADF7025 Rev. A | Page 5 of 44 Parameter Min Typ Max Unit Test Conditions CHANNEL FILTERING Adjacent Channel Rejection (Offset = ±1 × LP Filter BW Setting) 27 dB Second Adjacent Channel Rejection (Offset = ±2 × LP Filter BW Setting) 40 dB Desired signal (38.4 kbps DR, 200 kHz FDEV, ±300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3 Third Adjacent Channel Rejection (Offset = ±3 × LP Filter BW Setting) 43 dB Co-Channel Rejection −2 +24 dB Maximum rejection measured with CW interferer at center of channel Wideband Interference Rejection 70 dB Swept from 100 MHz to 2 GHz, measured as channel rejection BLOCKING ±1 MHz 42 dB ±2 MHz 51 dB ±10 MHz 64 dB Desired signal (38.4 kbps DR, 200 kHz FDEV, ±300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10−3 Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10−3 LNA Input Impedance 24 − j60 Ω FRF = 915 MHz, RFIN to GND 26 − j63 Ω FRF = 868 MHz 71 − j128 Ω FRF = 433 MHz RSSI Range at Input −100 to −36 dBm Linearity ±2 dB Absolute Accuracy ±3 dB Response Time 150 µs PHASE-LOCKED LOOP VCO Gain 65 MHz/V 902 MHz to 928 MHz band, VCO adjust = 3, VCO_BIAS_SETTING = 12 83 MHz/V 862 MHz to 870 MHz band, VCO adjust = 0, VCO_BIAS_SETTING = 10 Phase Noise (In-Band) −89 dBc/Hz PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 868 MHz, VCO_BIAS_SETTING = 10 Phase Noise (Out-of-Band) −110 dBc/Hz 1 MHz offset Residual FM 128 Hz From 200 Hz to 20 kHz, FRF = 868MHz PLL Settling Time 40 µs Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50kHz REFERENCE INPUT Crystal Reference 3.625 24 MHz External Oscillator 3.625 24 MHz Load Capacitance 33 pF Crystal Start-Up Time 1.0 ms Using 33 pF load capacitors Input Level CMOS levels TIMING INFORMATION Chip Enabled to Regulator Ready 10 µs CREG = 100 nF Crystal Oscillator Startup Time 1 ms With 19.2 MHz XTAL Tx to Rx Turnaround Time 150 µs + (5 × TBIT) Time to synchronized data, includes AGC settling |
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