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DM74S195 Scheda tecnica(PDF) 1 Page - National Semiconductor (TI) |
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DM74S195 Scheda tecnica(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF6476 June 1989 DM54S195DM74S195 4-Bit Parallel Access Shift Registers General Description These 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shiftload control input and a direct over- riding clear All inputs are buffered to lower the input drive requirements The registers have two modes of operation Parallel (broadside) load Shift (in the direction QA toward QD) Parallel loading is accomplished by applying the four bits of data and taking the shiftload control input low The data is loaded into the associated flip-flop and appears at the out- puts after the positive transition of the clock input During loading serial data flow is inhibited Shifting is accomplished synchronously when the shiftload control input is high Serial data for this mode is entered at the J-K inputs These inputs permit the first stage to perform as a J-K D or T-type flip-flop as shown in the truth table The high-performance S195 with a 105 MHz typical shift frequency is particularly attractive for very high-speed data processing systems In most cases existing systems can be upgraded merely by using this Schottky-clamped shift regis- ter Features Y Synchronous parallel load Y Positive-edge-triggered clocking Y Parallel inputs and outputs from each flip-flop Y Direct overriding clear Y J and K inputs to first stage Y Complementary outputs from last stage Y For use in high-performance accumulatorsprocessors serial-to-parallel parallel-to-serial converters Y Typical clock frequency 105 MHz Y Typical power dissipation 350 mW Connection Diagram Dual-In-Line Package TLF6476 – 1 Order Number DM54S195J or DM74S195N See NS Package Number J16A or N16E C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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