UC1606
65x132 Matrix LCD Controller-Drivers
Version 1.32
7
CONTROL REGISTERS
UC1606 contains registers which control the chip operation. These registers can be modified by commands.
The following table is a summary of the control registers, their meaning and their default value. The
commands supported by UC1606 are described in the next two sections, first a summary table, followed by
a detailed description.
Name:
The Symbolic reference of the register byte.
Note that, some symbol names refer to collection of bits (flags) within one register byte.
Default:
Numbers shown in Bold fonts are values after Power-Up-Reset and System-Reset.
Name
Bits
Default
Description
SL
6
0H
Start Line. Mapping from COM1 to Display Data RAM.
CR
8
0H
Return Column Address. Useful for cursor implementation.
CA
8
0H
Display Data RAM Column Address
(Used in Host to Display Data RAM access)
PA
4
0H
Display Data RAM Page Address
(Used in Host to Display Data RAM access)
BR
2
PIN
Bias Ratio. The ratio between VLCD and VBIAS.
Default value depends on BR[1:0] pin configuration,
and can be re-defined by Set LCD Bias Ratio command.
Bias Ratio (BR[1:0])
Mux Rate
00
01
10
11
65
7.33
8.0
8.66
9.33
49
6.0
6.67
7.33
8.0
33/25
4.67
5.33
6.0
6.66
TC
2
PIN
Temperature Compensation (per
oC).
00b: 0.0%
01b: -0.05%
10b: -0.1%
11b: -0.2%
Default value depends on TC[1:0] pin configuration.
GN
3
3H
Gain, coarse setting of VBIAS and VLCD
GN[2:0]
000 001 010 011 100 101 110 111
Gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72
PM
6
10H
Electronic Potentiometer to fine tune VBIAS and VLCD
MR
2
PIN
Multiplexing Rate: Number of pixel rows:
00b: 25
01b: 33
10b: 49
11b: 65
Default value depends on MR[1:0] pin configuration.