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UC1606
65x132 Matrix LCD Controller-Drivers
Version 1.32
5
Name
Type
Pins
Description
CONFIGURATION PIN
MR[1:0]
I
Multiplex Rate selection
“LL”: 25
“LH”: 33
“HL”: 49
“HH”: 65
BR[1:0]
I
LCD Bias Ratio. Four bias ratios are supported for each MR setting.
TC[1:0]
I
Temperature Compensation selection
“LL”: -0.0%
“LH”: -0.05%
“HL”: -0.1%
“HH”: -0.2%
HOST INTERFACE
PS[1:0]
I
Parallel/Serial.
Serial modes:
“LL”: serial (S8)
“LH”: serial (S9)
Parallel modes:
“HL”: 8080
“HH”: 6800
CS0
CS1
I
Chip Select. In parallel mode and S8 mode, chip is selected when CS0=”L”
and CS1=”H”. When the chip is not selected, D[7:0] may be high
impedance. *1
RST
I
When RST=”L”, all control registers are re-initialized by their default states.
When RST is not used, connect the pin to VDD.
CD
I
Select Command or Display Data for read/write operation. CD pin is not
used in S9 modes, connect it to VDD or VSS.
”L”: Command
”H”: Display data
WR0
WR1
I
WR[1:0] controls the read/write operation of the host interface.
In parallel mode, WR[1:0] meaning depends on whether the interface is in
the 6800 mode or the 8080 mode. In serial interface modes, these two pins
are not used. Connect to VSS.
D0~D7
I/O
Bi-directional bus for both serial and parallel host interfaces.
In S8 and S9 mode, leave unused pins open-circuit.
PS=1x
PS=0x
D0
D0
SCK
D1
D1
D2
D2
SDA
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7