ULTRACHIP
High-Voltage Mixed-Signal IC
©1999-2003
4
Product Specifications
PIN DESCRIPTION
Name
Type
Pins
Description
MAIN POWER SUPPLY
VDD
VDD2
VDD3
PWR
VDD2/VDD3 is the analog power supply and it should be connected to the
same power source. VDD is the digital power supply and it should be
connected to a voltage source that is no higher than VDD2/VDD3.
Minimize the trace resistance for VDD and VDD2/VDD3.
VSS
VSS2
GND
Ground. Connect VSS and VSS2 to the shared GND pin.
Minimize the trace resistance for VSS and VSS2.
LCD POWER SUPPLY
VB1+ VB1–
VB0+ VB0–
PWR
LCD Bias Voltages. These are the voltage sources to provide SEG
driving currents. These voltages are generated internally. Connect
capacitors of CBX value between VBX+ and VBX–.
The resistance of these four traces directly affects the SEG driving
strength of the resulting LCD module. Minimize the trace resistance is
critical in achieving high quality image.
VLCD-IN
VLCD-OUT
PWR
Main LCD Power Supply. Connect these pins together.
A by-pass capacitor CL is optional. When CL is used, connect CL
between VLCD and VSS, and keep the trace resistance under 300 Ohm.
NOTE
•
In COG applications, use one maximum width trace to connect VDD/VDD2/VDD3 to the LCM pad to
minimize trace resistance. However, to avoid noise cross-coupling, insert a slit, 0.2~0.3mm long,
between VDD/VDD2/VDD3. Same treatment for VSS/VSS2.
•
Recommended capacitor values:
CB: 150 ~ 250x LCD load capacitance or 1.0uF (2V), whichever is higher.
CL: 5nF ~ 20nF (16V) is appropriate for most applications.