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AD5290YRMZ10 Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD5290YRMZ10 Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 11 page Preliminary Technical Data AD5290 Rev. Pr C | Page 6 of 11 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 9 8 7 1 2 3 4 A B VSS W VDD SDO SDI GND 6 5 CLK CS TOP VIEW AD5290 Figure 2. AD5290 Pin Configuration Table 7. AD5290 Pin Function Descriptions Pin Menmonic Description 1 A A Terminal. VSS ≤ V A ≤ V DD 2 B B Terminal. VSS ≤ V B ≤ V DD 3 VSS Negative Supply. Connect to zero volts for single supply applications. 4 GND Digital Ground. 5 CS Chip Select Input, Active Low. When CS returns high, data will be loaded into the Wiper Register 6 CLK Serial Clock Input. Positive edge triggered 7 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. 8 SDO Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull- up resistor. It shifts out the previous 8 SDI bits that allows daisy-chain operation of multiple packages 9 VDD Positive Power Supply 10 W W Terminal. VSS ≤ V W ≤ V DD |
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