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ST22FJ1M Scheda tecnica(PDF) 3 Page - STMicroelectronics |
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ST22FJ1M Scheda tecnica(HTML) 3 Page - STMicroelectronics |
3 / 8 page 3/8 ST22FJ1M DESCRIPTION The ST22FJ1M is a member of the SmartJ™ plat- form using a 32-bit Reduced Instruction Set Com- puter (RISC) core to execute both Native RISC instructions and JavaCard™ 2.x Technology in- struction (byte codes) directly. Direct JavaCard™ byte code execution provides high performance advantage over processors that emulate the JavaCard™ byte code instruction set. – The product features a 24-bit wide linear ad- dressing capability and includes 768 Kbytes of User Flash, 16 KBytes of User RAM, 16 Kbytes of User secondary RAM, and 256 KBytes of User Page-Flash. – The Flash memory is organized in 12 sectors of 64 Kbytes each, with 8 Kbytes sub-sectors. Each sector can be erased in 1.5 s typical. All 32-bit words are programmed in 100 µs typical in User mode. One of the Flash sector is reserved by the HSI for saving data, when modifying a sector. The Page-Flash memory is organized in 128 sub-sectors of 2 Kbytes each. Each sub-sector can be erased in 50 ms typical. All 32-bit words are programmed in 200 µs typical in User mode. The secondary RAM memory can be used as a regular RAM, or dynamically mapped to the ad- dress of any of the 96 Flash sub-sectors, or mapped to two consecutive Flash sub-sectors. This memory can be used to speed-up process- ing and decrease power consumption. – The product includes a fast and secure Flash loader. The OS code is received from the OS manufacturer in an encrypted form, and decrypted on-chip before programming the Flash. Memory and Peripheral accesses are controlled by a Memory Protection Unit that allows to imple- ment firewalls between applications. Memories are accessed via two different buses, allowing simultaneous accesses to code and data. Memory load and stores can be performed at byte, short (2-bytes), or word (4-bytes) granularity, with optional pointer auto increment. The ST22 core includes dedicated DES instruc- tions for Secret Key cryptography, a fast Multiply and Accumulate instruction for Public Key cryptog- raphy (RSA) and Elliptic Curve cryptography. The ST22 core also includes specific instructions for security. The product has clock and power management, 2 User configurable Timers, a Central Interrupt Con- troller and a Random Number Generator. Figure 2. SmartJ™ Platform FLASH Architecture ST ROM FLASH RAM PERIPHERALS BUS 2 BUS 1 POWER MNGT. CLOCK MNGT. ISO 7816 SCP 160b/PRZ 32-bit RISC CORE P-FLASH SECONDARY RAM |
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