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MC100ES6014EJ Scheda tecnica(PDF) 2 Page - Freescale Semiconductor, Inc |
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MC100ES6014EJ Scheda tecnica(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 8 page Advanced Clock Drivers Device Data 2 Freescale Semiconductor MC100ES6014 Figure 1. 20-Lead Pinout (Top View) and Logic Diagram * Pins will default LOW when left open. ** Pins will default to VCC/2 when left open. * On next negative transition of CLK0 or CLK1 4 3 5 678 9 10 2 1 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. 17 18 16 15 14 13 12 11 19 20 10 D Q VCC EN VCC CLK1 CLK1 VBB CLK0 CLK0 CLK_SEL VEE Table 1. Pin Description Pin Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL Outputs CLK_SEL* ECL/PECL Active Clock Select Input EN* ECL Sync Enable VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply Table 2. Function Table CLK0 CLK1 CLK_SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* Table 3. General specifications Characteristics Value Internal Input Pulldown Resistor 75 k Ω Internal Input Pullup Resistor 75 k Ω ESD Protection Human Body Model Machine Model Charged Device Model > 2000 V > 200 V > 1500 V Thermal Resistance (Junction-to-Ambient) 0 LFPM, 20 TSSOP 500 LFPM, 20 TSSOP 140 °C/W 100 °C/W Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test |
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