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LM3203TLX Scheda tecnica(PDF) 11 Page - National Semiconductor (TI) |
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LM3203TLX Scheda tecnica(HTML) 11 Page - National Semiconductor (TI) |
11 / 15 page Operation Description (Continued) Circuit Operation Referring to Figure 1, the LM3203 operates as follows. Dur- ing the first part of each switching cycle, the control block in the LM3203 turns on the internal PFET (P-channel MOS- FET) switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of around ( V IN -VOUT ) / L, by storing energy in a magnetic field. During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (N-channel MOSFET) syn- chronous rectifier on. In response, the inductor’s magnetic field collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope around V OUT / L. The output filter capaci- tor stores charge when the inductor current is going high, and releases it when inductor current is going low, smooth- ing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. PWM Mode While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse width to control the peak inductor cur- rent. This is done by comparing the PFET drain current to a slope-compensated reference current generated by the error amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase in the load. The minimum on- time of PFET in PWM mode is 50ns (typ.). Bypass Mode The LM3203 contains an internal PFET switch for bypassing the PWM DC-DC converter during Bypass mode. In Bypass mode, this PFET is turned on to power the PA directly from the battery for maximum RF output power. Bypass mode is more efficient than operating in PWM mode at 100% duty cycle because the resistance of the bypass PFET is less than the series resistance of the PWM PFET and inductor. This translates into higher voltage available on the output in Bypass mode, for a given battery voltage. The part can be placed in bypass mode by sending BYP pin high. It remains in bypass mode until BYP pin goes low. It is recommended to connect BYPOUT pin directly to the output capacitor with a separate trace and not to the FB pin. Connect the BYPOUT pin to the V DD pin when Bypass mode is not required. If V CON is less than approx. 0.15V, the Bypass FET is turned off. Operating Mode Selection Control The LM3203 is designed for digital control of the operating modes using the BYP pin. Setting the BYP pin high (>1.2V) places the device in Bypass mode. Setting BYP pin low (<0.4V) forces operation in PWM mode. Bypass and PWM operation overlap during the transition between the two modes. This transition time is approxi- mately 31µs when changing from PWM to Bypass mode, and 15µs when changing from Bypass to PWM mode. This helps prevent under or overshoots during the transition pe- riod between PWM and Bypass modes. 20141636 FIGURE 1. Typical Operating System Circuit where baseband controls the output voltage using a DAC www.national.com 11 |
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