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AD10226 Scheda tecnica(PDF) 10 Page - Analog Devices

Il numero della parte AD10226
Spiegazioni elettronici  Dual-Channel, 12-Bit 125 MSPS IF Sampling A/D Converter
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

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AD10226
–10–
10MHz
= 52.22 – j0.421
50MHz
= 50.69 – j2.84
100MHz = 47.50 – j3.58
150MHz = 44.61 – j0.970
200MHz = 43.70 + j3.70
250MHz = 46.41 + j9.48
300MHz = 53.09 + j14.76
TPC 13. Input Impedance S11
FREQUENCY – MHz
0.1
1
10
1
2
3
4
5
6
7
8
9
10
0
100
1000
1MHz
= 1.010
10MHz = 1.028
50MHz = 1.045
100MHz = 1.066
140MHz = 1.090
160MHz = 1.126
200MHz = 1.170
TPC 14. Voltage Standing Wave Ratio (VSWR)
Equivalent Circuits
VCC
24k
8k
ENCODE
ENCODE
8k
24k
Test Circuit 1. Equivalent ENCODE Input
VCC
100
DIGITAL
OUTPUT
Test Circuit 2. Equivalent Digital Output
Q1
NPN
VREF OUTPUT
VCC
VCC
Test Circuit 3. Equivalent Voltage Reference Output
VCC
AIN2
15k
50
3.75k
AIN1
15k
3.75k
Test Circuit 4. Equivalent Analog Input
DEFINITION OF TERMS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point on the rising edge of the ENCODE
command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
ENCODE Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these specs
define an acceptable ENCODE duty cycle.


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