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MC74VHCT74ADT Scheda tecnica(PDF) 3 Page - ON Semiconductor |
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MC74VHCT74ADT Scheda tecnica(HTML) 3 Page - ON Semiconductor |
3 / 6 page MC74VHCT74A VHC Data – Advanced CMOS Logic DL203 — Rev 2 3 MOTOROLA AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) Sb l P T C di i TA = 25°C TA = – 40 to 85°C Ui Symbol Parameter Test Conditions Min Typ Max Min Max Unit tPLH, tPHL Maximum Propagation Delay, CP to Q or Q VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 5.8 6.3 7.8 8.8 1.0 1.0 9.0 10.0 ns tPLH, tPHL Maximum Propagation Delay, SD or RD to Q or Q VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 7.6 8.1 10.4 11.4 1.0 1.0 12.0 13.0 ns fmax Maximum Clock Frequency (50% Duty Cycle) VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 100 80 160 140 80 65 MHz Cin Maximum Input Capacitance 4 10 10 pF C P Di i i C i (N NO TAG) Typical @ 25 °C, VCC = 5.0V F CPD Power Dissipation Capacitance (Note NO TAG) 24 pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip–flop). CPD is used to determine the no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. TIMING REQUIREMENTS (Input tr = tf = 3.0ns) Sb l P V Guaranteed Limit Ui Symbol Parameter VCC V TA = 25_C TA = – 40 to 85 _C Unit tw Minimum Pulse Width, CP 5.0 ± 0.5 5.0 5.0 ns tw Minimum Pulse Width, RD or SD 5.0 ± 0.5 5.0 5.0 ns tsu Minimum Setup Time, D to CP 5.0 ± 0.5 5.0 5.0 ns th Minimum Hold Time, D to CP 5.0 ± 0.5 0.0 0.0 ns trec Minimum Recovery Time, SD or RD to CP 5.0 ± 0.5 3.5 3.5 ns |
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