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CA5130 Scheda tecnica(PDF) 7 Page - Intersil Corporation

Il numero della parte CA5130
Spiegazioni elettronici  15MHz, BiMOS Microprocessor Operational Amplifiers with MOSFET Input/CMOS Output
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA5130 Scheda tecnica(HTML) 7 Page - Intersil Corporation

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7
Offset Nulling
Offset voltage nulling is usually accomplished with a 100,000
potentiometer connected across Terminals 1 and 5 and with the
potentiometer slider arm connected to Terminal 4. A fine offset
null adjustment usually can be effected with the slider arm
positioned in the midpoint of the potentiometer's total range.
Input Current Variation with Temperature
The input current of the CA5130 Series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate protective diodes in the input
circuit. As with any semiconductor junction device, including
op amps with a junction FET input stage, the leakage current
approximately doubles for every 10oC increase in
temperature. Figure 25 provides data on the typical variation
of input bias current as a function of temperature in the
CA5130.
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA5130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat-
sinking can also very markedly reduce and stabilize input
current variations.
Input Offset Voltage (VIO) Variation with DC Bias vs
Device Operating Life
It is well known that the characteristics of a MOS/FET device
can change slightly when a DC gate source bias potential is
applied to the device for extended time periods. The
magnitude of the change is increased at high temperatures.
Users of the CA5130 should be alert to the possible impacts
of this effect if the application of the device involves extended
operation at high temperatures with a significant differential
DC bias voltage applied across Terminals 2 and 3. Figure 26
shows typical data pertinent to shifts in offset voltage
encountered with CA5130 devices (metal can package)
during life testing. At lower temperatures (metal can and
plastic packages), for example at 85oC, this change in voltage
is considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2V differential voltage
example represents conditions when the amplifier output
stage is “toggled”, e.g., as in comparator applications.
Power-Supply Considerations
Because the CA5130 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 1A and 1B show the
CA5130 connected for both dual and single supply operation.
Dual supply operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q8 and Q12 are driven
increasingly positive with respect to ground, current flow
through Q12 (from the negative supply) to the load is
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
Single supply operation: Initially, let it be assumed that the
value of RL is very high (or disconnected), and that the input
terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage drops across
Q8 and Q12 are of equal magnitude. Figure 16 shows typical
quiescent supply current vs supply voltage for the CA5130
operated under these conditions. Since the output stage is
operating as a Class A amplifier, the supply current will remain
constant under dynamic operating conditions as long as the
transistors are operated in the linear portion of their voltage
transfer characteristics (see Figure 15). If either Q8 or Q12 are
swung out of their linear regions toward cutoff (a nonlinear
region), there will be a corresponding reduction in supply
current. In the extreme case, e.g., with Terminal 8 swung down
to ground potential (or tied to ground), NMOS transistor Q12 is
completely cut off and the supply current to series connected
3
2
8
4
7
6
RL
V+
Q8
Q12
CA5130
+
-
FIGURE 1A. DUAL POWER SUPPLY OPERATION
V-
3
2
8
4
7
6
RL
Q8
Q12
CA5130
+
-
FIGURE 1B. SINGLE POWER SUPPLY OPERATION
FIGURE 1. CA5130 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
V+
CA5130, CA5130A


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