Motore di ricerca datesheet componenti elettronici |
|
PCM1840 Scheda tecnica(PDF) 13 Page - Texas Instruments |
|
|
PCM1840 Scheda tecnica(HTML) 13 Page - Texas Instruments |
13 / 34 page 1 0 N-1 N-2 Left (Ch1) Slot-0 (Word Length : 32) 1 0 N-1 N-2 BCLK SDOUT n th Sample (n+1) th Sample 1 0 N-1 Right (Ch2) Slot-0 (Word Length : 32) Left (Ch1) Slot-0 (Word Length : 32) FSYNC N-2 1 0 N-1 N-2 BCLK SDOUT n th Sample (64 BCLK Cycles) (n+1) th Sample (64 BCLK Cycles) 1 0 N-1 FSYNC N-2 1 0 1 0 N-1 N-2 1 0 N-1 N-2 Left (Ch1) Slot-0 (Word Length : 32) Right (Ch2) Slot-0 (Word Length : 32) Left (Ch1) Slot-0 (Word Length : 32) Right (Ch2) Slot-0 (Word Length : 32) 1 0 N-1 N-2 1 0 N-1 N-2 BCLK SDOUT n th Sample (n+1) th Sample 1 0 N-1 FSYNC N-2 Left (Ch1) Slot-0 (Word Length : 32) Right (Ch2) Slot-0 (Word Length : 32) Left (Ch1) Slot-0 (Word Length : 32) 13 PCM1840 www.ti.com SBAS989 – APRIL 2019 Product Folder Links: PCM1840 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Figure 18. I2S Mode Protocol Timing in Slave Mode Figure 19. I2S Protocol Timing In Master Mode For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the 32-bits word length of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the 32- bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles. 7.3.2.3 Left-Justified (LJ) Interface The standard LJ protocol is defined for only two channels: left and right. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. The MSB of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is transmitted on the rising edge of BCLK. Figure 20 and Figure 21 illustrate the protocol timing for LJ operation in slave and master mode of operation. Figure 20. LJ Mode Protocol Timing In Slave Mode |
Codice articolo simile - PCM1840 |
|
Descrizione simile - PCM1840 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |