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MSP430FR6007 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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MSP430FR6007 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 179 page 9 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3 – MARCH 2020 Submit Documentation Feedback Product Folder Links: MSP430FR6007 MSP430FR6005 Terminal Configuration and Functions Copyright © 2020, Texas Instruments Incorporated (1) The signal that is listed first for each pin is the reset default pin name. (2) To determine the pin mux encodings for each pin, see Section 6.14. (3) Signal Types: I = Input, O = Output, I/O = Input or Output. (4) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details) (5) The power source shown in this table is the I/O power source, which may differ from the module power source. (6) Reset States: OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled PU = Pullup is enabled PD = Pulldown is enabled N/A = Not applicable 4.2 Pin Attributes Table 4-1 lists the attributes of each pin. Table 4-1. Pin Attributes PIN NUMBER SIGNAL NAME(1) (2) SIGNAL TYPE(3) BUFFER TYPE(4) POWER SOURCE(5) RESET STATE AFTER BOR(6) 1 P2.2 I/O LVCMOS DVCC OFF COUT O LVCMOS DVCC – UCA0CLK I/O LVCMOS DVCC – A14 I Analog DVCC – C14 I Analog DVCC – 2 P2.3 I/O LVCMOS DVCC OFF TA0.0 I/O LVCMOS DVCC – UCA0STE I/O LVCMOS DVCC – A15 I Analog DVCC – C15 I Analog DVCC – 3 P1.0 I/O LVCMOS DVCC OFF UCA1CLK I/O LVCMOS DVCC – TA1.0 I/O LVCMOS DVCC – A0 I Analog DVCC – C0 I Analog DVCC – VREF- O Analog DVCC – VeREF- I Analog DVCC – 4 P1.1 I/O LVCMOS DVCC OFF UCA1STE I/O LVCMOS DVCC – TA4.0 I/O LVCMOS DVCC – A1 I Analog DVCC – C1 I Analog DVCC – VREF+ O Analog DVCC – VeREF+ I Analog DVCC – 5 AVSS2 P Power – N/A 6 PJ.4 I/O LVCMOS DVCC OFF LFXIN I Analog DVCC – 7 PJ.5 I/O LVCMOS DVCC OFF LFXOUT O Analog DVCC – 8 AVSS3 P Power – N/A 9 PJ.6 I/O LVCMOS DVCC – HFXIN I Analog DVCC – 10 PJ.7 I/O LVCMOS DVCC OFF HFXOUT O Analog DVCC – 11 AVSS4 P Power – N/A |
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