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MSP430FG479 Scheda tecnica(PDF) 55 Page - Texas Instruments |
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MSP430FG479 Scheda tecnica(HTML) 55 Page - Texas Instruments |
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55 / 97 page  55 MSP430FG479, MSP430FG478, MSP430FG477 www.ti.com SLAS580E – OCTOBER 2008 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430FG479 MSP430FG478 MSP430FG477 Detailed Description Copyright © 2008–2020, Texas Instruments Incorporated 6.9 Peripherals Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide. 6.9.1 Oscillator and System Clock The clock system is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency crystal oscillator (XT1), plus a 8-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals: • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal • Main clock (MCLK), the system clock used by the CPU • Submain clock (SMCLK), the subsystem clock used by the peripheral modules • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8 6.9.2 Brownout, Supply Voltage Supervisor (SVS) The brownout circuit provides the proper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must make sure the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min). 6.9.3 Digital I/O There are six 8-bit I/O ports implemented—ports P1 through P6: • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. • Read and write access to port-control registers is supported by all instructions 6.9.4 Watchdog Timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. 6.9.5 Basic Timer1 and Real-Time Clock The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated real- time clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap- year correction. |
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