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MSP430F5310 Scheda tecnica(PDF) 34 Page - Texas Instruments |
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MSP430F5310 Scheda tecnica(HTML) 34 Page - Texas Instruments |
34 / 109 page SDA SCL t HD,DAT t SU,DAT t HD,STA t HIGH t LOW t BUF t HD,STA t SU,STA t SP t SU,STO 34 MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304 SLAS677G – SEPTEMBER 2010 – REVISED MAY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304 Specifications Copyright © 2010–2020, Texas Instruments Incorporated 5.33 USCI (I 2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-11) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT fUSCI USCI input clock frequency Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% fSYSTEM MHz fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz tHD,STA Hold time (repeated) START fSCL ≤ 100 kHz 2.2 V, 3 V 4.0 µs fSCL > 100 kHz 0.6 tSU,STA Setup time for a repeated START fSCL ≤ 100 kHz 2.2 V, 3 V 4.7 µs fSCL > 100 kHz 0.6 tHD,DAT Data hold time 2.2 V, 3 V 0 ns tSU,DAT Data setup time 2.2 V, 3 V 250 ns tSU,STO Setup time for STOP fSCL ≤ 100 kHz 2.2 V, 3 V 4.0 µs fSCL > 100 kHz 0.6 tSP Pulse duration of spikes suppressed by input filter 2.2 V 50 600 ns 3 V 50 600 Figure 5-11. I2C Mode Timing |
Codice articolo simile - MSP430F5310_V01 |
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Descrizione simile - MSP430F5310_V01 |
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