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MSP430F2619 Scheda tecnica(PDF) 85 Page - Texas Instruments |
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MSP430F2619 Scheda tecnica(HTML) 85 Page - Texas Instruments |
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85 / 120 page  P5SEL.x P5DIR.x P5IN.x Module X IN Module X OUT P5OUT.x P5REN.x P5.0/UCB1STE/UCA1CLK P5.1/UCB1SIMO/UCB1SDA P5.2/UCB1SOMI/UCB1SCL P5.3/UCB1CLK/UCA1STE P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOUTH/SVSOUT Module Direction Direction 0: Input 1: Output D EN DVSS DVCC Pad Logic 1 1 0 1 0 1 0 85 MSP430F2619, MSP430F2618, MSP430F2617, MSP430F2616 MSP430F2419, MSP430F2418, MSP430F2417, MSP430F2416 www.ti.com SLAS541L – JUNE 2007 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430F2619 MSP430F2618 MSP430F2617 MSP430F2616 MSP430F2419 MSP430F2418 MSP430F2417 MSP430F2416 Detailed Description Copyright © 2007–2020, Texas Instruments Incorporated Table 6-19. Port P4 (P4.0 to P4.7) Pin Functions (continued) PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS(1) P4DIR.x P4SEL.x P4.4/TB4 4 P4.4 (I/O) 0 = Input 1 = Output 0 Timer_B7.CCI4A and Timer_B7.CCI4B 0 1 Timer_B7.TB4 1 1 P4.5/TB5 5 P4.5 (I/O) 0 = Input 1 = Output 0 Timer_B7.CCI5A and Timer_B7.CCI5B 0 1 Timer_B7.TB5 1 1 P4.6/TB6 6 P4.6 (I/O) 0 = Input 1 = Output 0 Timer_B7.CCI6A and Timer_B7.CCI6B 0 1 Timer_B7.TB6 1 1 P4.7/TBCLK 7 P4.7 (I/O) 0 = Input 1 = Output 0 Timer_B7.TBCLK 0 1 (1) X = Don't care (2) The pin direction is controlled by the USCI module. (3) UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI_B1 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. 6.10.6 Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger Figure 6-11 shows the port diagram. Table 6-20 summarizes the selection of the pin function. Figure 6-11. Port P5 (P5.0 to P5.7) Diagram Table 6-20. Port P5 (P5.0 to P5.7) Pin Functions PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1) P5DIR.x P5SEL.x P5.0/UCB1STE/ UCA1CLK 0 P5.0 (I/O) 0 = Input 1 = Output 0 UCB1STE/UCA1CLK(2)(3) X 1 |
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