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X1228S14-2.7A Scheda tecnica(PDF) 7 Page - Intersil Corporation |
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X1228S14-2.7A Scheda tecnica(HTML) 7 Page - Intersil Corporation |
7 / 29 page 7 FN8100.2 October 17, 2005 Write Cycle Timing Power-up Timing Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec. (2) Typical values are for TA = 25°C and VCC = 5.0V Nonvolatile Write Cycle Timing Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS Watchdog/Low Voltage Reset Parameters (SeeFigures 3 and 4) SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start Condition Symbol Parameter Min. Typ.(2) Max. Units tPUR(1) Time from Power-up to Read 1 ms tPUW(1) Time from Power-up to Write 5 ms Symbol Parameter Min. Typ.(1) Max. Units tWC(1) Write Cycle Time 5 10 ms Symbols Parameters Min. Typ. Max. Unit VPTRIP Programmed Reset Trip Voltage X1228-4.5A X1228 X1228-2.7A X1228-2.7 4.50 4.25 2.75 2.55 4.63 4.38 2.85 2.65 4.75 4.50 2.95 2.75 V tRPD VCC Detect to RESET LOW 500 ns tPURST Power-up Reset Time-out Delay 100 250 400 ms tF VCC Fall Time 10 µs tR VCC Rise Time 10 µs tWDO Watchdog Timer Period (Crystal = 32.768kHz): WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 1, WD0 = 0 1.7 725 225 1.75 750 250 1.8 775 275 s ms ms tRST Watchdog Reset Time-out Delay (Crystal=32.768kHz) 225 250 275 ms tRSP 2-Wire interface 1 µs VRVALID Reset Valid VCC 1.0 V X1228 |
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