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MC1495BP Scheda tecnica(PDF) 7 Page - ON Semiconductor |
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MC1495BP Scheda tecnica(HTML) 7 Page - ON Semiconductor |
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7 / 16 page  MC1495 http://onsemi.com 7 OPERATION AND APPLICATIONS INFORMATION Theory of Operation The MC1495 is a monolithic, four-quadrant multiplier which operates on the principle of variable transconductance. A detailed theory of operation is covered in Application Note AN489, Analysis and Basic Operation of the MC1595. The result of this analysis is that the differential output current of the multiplier is given by: 2VXVY RXRYI3 IA – IB = ∆I = where, IA and IB are the currents into Pins 14 and 2, respectively, and VX and VY are the X and Y input voltages at the multiplier input terminals. DESIGN CONSIDERATIONS General The MC1495 permits the designer to tailor the multiplier to a specific application by proper selection of external components. External components may be selected to optimize a given parameter (e.g. bandwidth) which may in turn restrict another parameter (e.g. maximum output voltage swing). Each important parameter is discussed in detail in the following paragraphs. Linearity, Output Error, ERX or ERY Linearity error is defined as the maximum deviation of output voltage from a straight line transfer function. It is expressed as error in percent of full scale (see figure below). VO +10 V VE(max) +10V Vx or Vy For example, if the maximum deviation, VE(max), is ±100 mV and the full scale output is 10 V, then the percentage error is: VE(max) VO(max) ER = x 100 = 100 x 10–3 10 x 100 = ±1.0%. Linearity error may be measured by either of the following methods: 1. Using an X-Y plotter with the circuit shown in Figure 5, obtain plots for X and Y similar to the one shown above. 2. Use the circuit of Figure 4. This method nulls the level shifted output of the multiplier with the original input. The peak output of the null operational amplifier will be equal to the error voltage, VE (max). One source of linearity error can arise from large signal nonlinearity in the X and Y input differential amplifiers. To avoid introducing error from this source, the emitter degeneration resistors RX and RY must be chosen large enough so that nonlinear base-emitter voltage variation can be ignored. Figures 17 and 18 show the error expected from this source as a function of the values of RX and RY with an operating current of 1.0 mA in each side of the differential amplifiers (i.e., I3 = I13 = 1.0 mA). 3 dB Bandwidth and Phase Shift Bandwidth is primarily determined by the load resistors and the stray multiplier output capacitance and/or the operational amplifier used to level shift the output. If wideband operation is desired, low value load resistors and/or a wideband operational amplifier should be used. Stray output capacitance will depend to a large extent on circuit layout. Phase shift in the multiplier circuit results from two sources: phase shift common to both X and Y channels (due to the load resistor-output capacitance pole mentioned above) and relative phase shift between X and Y channels (due to differences in transadmittance in the X and Y channels). If the input to output phase shift is only 0.6 °, the output product of two sine waves will exhibit a vector error of 1%. A 3 ° relative phase shift between VX and VY results in a vector error of 5%. Maximum Input Voltage VX(max), VY(max) input voltages must be such that: VX(max) <I13 RY VY(max) <I3 RY Exceeding this value will drive one side of the input amplifier to “cutoff” and cause nonlinear operation. Current I3 and I13 are chosen at a convenient value (observing power dissipation limitation) between 0.5 mA and 2.0 mA, approximately 1.0 mA. Then RX and RY can be determined by considering the input signal handling requirements. 2VX VY RX RY I3 1.0 mA 10 V RX = RY > = 10 k Ω. The equation IA – IB = For VX(max) = VY(max) = 10 V; is derived from IA – IB = 2VX VY (RX + 2kT qI13 ) (RY + 2kT qI3 ) I3 with the assumption RX >> 2kT qI13 and RY >> 2kT qI3 . At TA = +25°C and I13 = I3 = 1.0 mA, 2kT qI13 2kT qI3 = = 52 Ω. Therefore, with RX = RY = 10 kΩ the above assumption is valid. Reference to Figure 19 will indicate limitations of VX(max) or VY(max) due to V1 and V7. Exceeding these limits will cause saturation or “cutoff” of the input transistors. See Step 4 of General Design Procedure for further details. |
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