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DLPC900 Scheda tecnica(PDF) 39 Page - Texas Instruments |
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DLPC900 Scheda tecnica(HTML) 39 Page - Texas Instruments |
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39 / 83 page  Port 1 Port 2 Peripherals GPIO I2C USB PWM UART Memory Controller DRAM SSP DMD Controller Pixel Data Processing CPU BUS MEMORY DMA BUS Formatter LED Triggers Pattern Sequencer ARM PLL Reset JTAG ICE Clock RAM Flash Interface Digital Input PLLD PLLM PLLS Crystal POSENSE PWRGOOD JTAG LED Triggers DMD Control and Data Interface Debug PWM USB I2C GPIO Digital Input GND VDD33 VDDC VDD18 DMD Serial Interface 39 DLPC900 www.ti.com DLPS037D – OCTOBER 2014 – REVISED MARCH 2019 Product Folder Links: DLPC900 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated 7 Detailed Description 7.1 Overview The DLPC900 controller processes the digital input image and converts the data into the digital format needed by the DLP9000 or the DLP6500. The DLP9000 and the DLP6500 reflect light by using binary pulse-width- modulation (PWM) for each micromirror. For further details, refer to the DLP9000 or the DLP6500 data sheets. The DLPC900 combined with a DLP6500 supports a wide variety of resolutions from SVGA to 1080p. When accurate pattern display is needed, a native 1080p resolution source is used for a one-to-one association with the corresponding micromirror on the DLP6500. The DLPC900 combined with a DLP9000 supports only native WQXGA resolution for a one-to-one association with the corresponding micromirror on the DLP9000. Both combinations are well-suited for structured light, additive manufacturing, or digital exposure applications. 7.2 Functional Block Diagram Figure 15. Functional Block Diagram |
Codice articolo simile - DLPC900_V01 |
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Descrizione simile - DLPC900_V01 |
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