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RTQ2532W Scheda tecnica(PDF) 18 Page - Richtek Technology Corporation |
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RTQ2532W Scheda tecnica(HTML) 18 Page - Richtek Technology Corporation |
18 / 20 page RTQ2532W 18 DSQ2532W-00 July 2019 www.richtek.com © Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 9. PCB Layout Guide surface for good thermal dissipation. Using vias and long power traces for the input and output capacitors connections is not recommended and has negative effects on performance. Figure 9 shows a layout example that reduces conduction trace loops, helping to minimize inductive parasitics and load transient effects while improving the circuit stability. R1 21 GND R2 Load PGOOD reference supply Input Power Plane Output Power Plane Ground Power Plane Ground Power Plane for Thermal Dissipation / Signal Ground To Signal Ground PG Output CFF CNR/SS R3 CIN COUT Thermal vias can help to reduce power trace and improve thermal dissipation. Place capacitors as close as possible to the connected pins for minimizing power loop area and low Impedance connection to GND late. VOUT SNS FB PGOOD 50mV VIN EN NC 1.6V NR/SS 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 17 16 20 18 19 |
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