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MC100ES7111 Scheda tecnica(PDF) 2 Page - Motorola, Inc |
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MC100ES7111 Scheda tecnica(HTML) 2 Page - Motorola, Inc |
2 / 8 page MC100ES7111 MOTOROLA TIMING SOLUTIONS 2 Q8 Q7 Q0 Q1 Figure 1. MC100ES7111 Logic Diagram VCC Q2 Q1 Q0 VCC Q7 Q9 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1234 5678 24 23 22 21 20 19 18 17 16 MC100ES7111 Figure 2. 32–Lead Package Pinout (Top View) VCC VCC Q9 Q8 Q2 0 1 CLK0 CLK0 CLK1 CLK1 CLK_SEL VCC VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 OE OE Table 1. PIN CONFIGURATION Pin I/O Type Function CLK0, CLK0 Input HSTL/LVDS Differential HSTL or LVDS reference clock signal input CLK1, CLK1 Input PECL Differential PECL reference clock signal input CLK_SEL Input LVCMOS Reference clock input select OE Input LVCMOS Output enable/disable. OE is synchronous to the input reference clock which eliminates possible output runt pulses when the OE state is changed. Q[0–9], Q[0–9] Output LVDS Differential clock outputs GND Supply Negative power supply VCC Supply Positive power supply of the device (3.3V) Table 2. FUNCTION TABLE Control Default 0 1 CLK_SEL 0 CLK0, CLK0 (HSTL/LVDS) is the active differential clock input CLK1, CLK1 (PECL) is the active differential clock input OE 0 Q[0-9], Q[0-9] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses. Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses. |
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