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MC10107 Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC10107 Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 5 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–30 REV 5 © Motorola, Inc. 1996 3/93 Triple 2-Input Exclusive OR/ Exclusive NOR Gate The MC10107 is a triple–2 input exclusive OR/NOR gate. PD = 40 mW typ/gate (No Load) tpd = 2.8 ns typ tr, tf = 2.5 ns typ (20%–80%) LOGIC DIAGRAM VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 15 13 14 9 4 12 10 11 3 2 7 5 3 = (4 • 5) + (4 • 5) 2 = (4 • 5) + (4 • 5) MC10107 DIP PIN ASSIGNMENT VCC1 AOUT AOUT AIN AIN *NC BIN VEE VCC2 CIN CIN COUT COUT BOUT BOUT BIN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 *NC = No Connection Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 |
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