© Semiconductor Components Industries, LLC, 2000

May, 2000 – Rev. 1

1

Publication Order Number:

MC100LVEP14/D

MC100LVEP14

Low-Voltage 1:5 Differential

LVECL/LVPECL/LVEPECL/HSTL

Clock Driver

The MC100LVEP14 is a low skew 1–to–5 differential driver, designed

with clock distribution in mind, accepting two clock sources into an input

multiplexer. The LVECL/LVPECL input signals can be either differential

or single–ended (if the VBB output is used). HSTL inputs can be used

when the LVEP14 is operating under LVPECL conditions.

The LVEP14 specifically guarantees low output–to–output skew.

Optimal design, layout, and processing minimize skew within a device and

from lot to lot.

To ensure that the tight skew specification is realized, both sides of

any differential output need to be terminated identically into 50

W even

if only one side is being used. When fewer than all five pairs are used,

identically terminate all the output pairs on the same package side

whether used or unused. If no outputs on a single side are used, then

leave these outputs open (unterminated). This will maintain minimum

output skew. Failure to do this will result in a 10–20ps loss of skew

margin (propagation delay) in the output(s) in use.

The common enable (EN) is synchronous, outputs are enabled/

disabled in the LOW state. This avoids a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control. The internal flip flop is clocked on the falling edge of the input

clock, therefore all associated specification limits are referenced to the

negative edge of the clock input.

The MC100LVEP14, as with most other LVECL devices, can be

operated from a positive VCC supply in LVPECL mode. This allows

the LVEP14 to be used for high performance clock distribution in

+3.3V or +2.5V systems. Single ended input operation is limited to a

VCC ≥ 3.0V in LVPECL mode, or VEE ≤ –3.0V in LVECL mode.

Designers can take advantage of the LVEP14’s performance to

distribute low skew clocks across the backplane or the board. For more

information, refer to Application Note AN1406/D.

For Additional Information, See Application Note AND8003/D

http://onsemi.com

Device

Package

Shipping

ORDERING INFORMATION

MC100LVEP14DT

TSSOP

75 Units/Tray

MC100LVEP14DTR2

TSSOP

2500 Tape & Reel

TSSOP–20

DT SUFFIX

CASE 948E

MARKING DIAGRAM*

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

*For additional information, see Application Note

AND8002/D

100

VP14

ALYW

20

1

VP = LVEP